Physical Design Engineer

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > GPU ASICS Engineering

General Summary:

Physical implementation of industry leading integrated graphics core designs from netlist to GDS of very complex and high frequency blocks or top level. This includes floor-planning, placement, clock implementation and routing of very high gate count design to meet very aggressive Power, Performance and Area (PPA) targets. Involves working on latest technology process nodes and employing latest design techniques to push PPA envelope which includes working with RTL design teams to optimize design. Incumbent is also expected to be involved in collaboration with multi-disciplined teams and tool vendors to develop/enhance automation in flows and methodologies for design efficiency improvement. This role requires understanding of trade-offs to be made for PPA, hence decisions taken to get the optimal design.

The ideal candidate will have/demonstrate the following:

• Experience in Physical design which includes floor-planning, placement, clock implementation, routing for complex, high frequency designs

• Experience with physical synthesis and implementation tools - Synopsys Fusion Compiler, ICC2 and Cadence Genus/Innovus

• Must have good knowledge of static timing analysis, reliability and power analysis

• Strong understanding of CMOS circuit design and design techniques to push Power, Performance and Area of complex designs

• Ability to think outside the box for innovative solutions to improve power and eliminate performance bottlenecks

• Strong understanding of GPU micro-architecture and collaborate with RTL designers to improve bottlenecks for power and performance

• Solid working knowledge of scripting skills including tcl, perl or python

• Excellent communication skills and collaborating in a team environment is a must

Preferred Skills:

• Clock, power delivery network design, process technology, prior experience in flow and methodology development, block closure

• Hands on experience with Synthesis, DFT, Place and Route, Timing and Reliability Signoff

• Hands on experience working with very complex designs that push the envelope of Power, Performance and Area

• Hands on experience working with sub-micron technology process nodes eg. 5nm, 4nm and below is highly advantageous

• Prior experience in flow and methodology development is an advantage

• RTL expertise (Verilog/System Verilog)

• Excellent debug and analytical skills

• Ability to work well in a collaborative environment with multi-disciplined teams

Minimum Qualifications:

• Bachelor's degree in Electrical/Computer Engineering

• 3+ years of direct physical design work experience

• Strong background in VLSI design, scripting

• Strong background and experience working with industry standard Synthesis and Place and Route tools including Signoff tools

• Hands on experience taping out designs in sub-micron technology node design < 10nm

• Expect strong self-motivation and time management skills

Preferred Qualifications:

• Master's degree in Electrical/Computer Engineering

• 6+ years of direct physical design work experience

• In depth end to end experience from RTL2GDS, taping out at least 4 complex designs

Minimum Qualifications:

• Bachelor's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 4+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

OR

Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or related field and 3+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

OR

PhD in Computer Engineering, Computer Science, Electrical Engineering, or related field and 2+ years of Software Engineering, Hardware Engineering, Systems Engineering, or related work experience.

Although this role has some expected minor physical activity, this should not deter otherwise qualified applicants from applying. If you are an individual with a physical or mental disability and need an accommodation during the application/hiring process, please call Qualcomm's toll-free number found here (~~~) for assistance. Qualcomm will provide reasonable accommodations, upon request, to support individuals with disabilities as part of our ongoing efforts to create an accessible workplace.

Qualcomm is an equal opportunity employer and supports workforce diversity.

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EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range:

$151,000.00 - $227,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer!

If you would like more information about this role, please contact Qualcomm Careers (~~~) .

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification