PDK Specifications Developer Intern

Job Description

The Team Design Enablement (DE) is one of the key pillars enabling Intel to deliver winning products. DE's mission is to enable all Intel product design teams to get to market faster with leadership products. The Process Design Kit Group (PDK) within DE delivers Intel process technology PDKs that are optimized to work with industry standard EDA tools.

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In this role, you will work with experts helping them to define requirements and specifications for the PDKs. The specifications need to capture the requirements for the PDK components and the interoperability between the components. Especially, you will focus on 3DIC design and verification of unit test structures and building automation to systematically generate the designs and improve the QA coverage.

You will use modern scripting languages (like Python and TCL) to generate and interpret the test structures, specifications, and associated reports.

The successful candidate should exhibit the following behavioral traits

Creative thinker that is self-motivated and collaborates well with peers and expert leaders.

This is a 3-month internship with possible extension and compensation will be given accordingly based on candidate education level and internship duration. Job assignments are usually for the summer or for short periods during breaks from school.

#DesignEnablement

Qualifications

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

Candidate must be actively pursuing a master's degree in electrical engineering or other related field of study.

University course work in the following areas

-VLSI, Circuit layout, transistor's type, and usage

-Software development

Preferred Qualifications

6+ months of knowledge in one or more of the following:

Understanding of electrical circuit design and simulation and or physical design understanding of semiconductor physics and technology.

Understanding of 3DIC basics, configurations, and concepts.

Python programming

Exposure to Calibre SVRF and TVF, or Synopsys ICV, or Cadence Pegasus. Exposure to layout and/or schematic entry using Cadence Virtuoso and/or Synopsys Custom Designer.

Open for students pursuing a PhD in Electrical Engineering or other related field of study looking to get exposure to Intel technology, PDK development and QA, and 3DIC technologies.

Inside this Business Group

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth.

Other Locations

US, TX, Austin; US, AZ, Phoenix; US, CA, Folsom; US, CA, Santa Clara

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Benefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here. (~~~)

Annual Salary Range for jobs which could be performed in US, California: $63,000.00-$166,000.00

*Salary range dependent on a number of factors including location and experience

Working Model

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. In certain circumstances the work model may change to accommodate business needs.